As semiconductor technology continues to inch closer to practical limitations in terms of feature size, architects are increasingly focusing on alternative manners of meeting the demands for integrating increasingly complex circuitry onto semiconductor devices, or chips. In addition, as feature sizes decrease, and thus as faster and more complex circuits are integrated onto a given semiconductor chip, architects are finding that in many instances the communication of data between the various functional units on a semiconductor chip can become a bottleneck on overall performance. Communicating data between functional units disposed at opposite ends of a large semiconductor chip (e.g., a 300 or 500 mm2 die size) often requires several clock cycles, as well as significant buffering logic on the chip. Furthermore, in general as the size and amount of circuitry integrated into a chip design increases, the yield of the manufacturing process typically decreases, thereby increasing the cost of the manufactured chips.
One proposed solution to address these limitations has been to physically and electrically couple together multiple semiconductor chips or dies into a stack arrangement. By doing so, individual chips that are smaller, less complex, and less expensive can be used in lieu of a single larger, more complex and more expensive chip, and often with comparable or better overall performance. In many instances, for example, it has been found that the vertical distance between circuit logic disposed in different layers of a multi-layer semiconductor stack may end up being shorter than the maximum horizontal distances within any given circuit layer, and as such, communicating data between circuit layers disposed on different chips may involve less latency than communicating data between distant points on the same chip. Some conventional stacking technologies, for example, are capable of separating circuit layers on adjacent dies in a stack by less than 100 um, which is an order of magnitude or more less than the maximum horizontal dimension of many dies (e.g., a 100 mm2 die has a length and width of 10,000 um).
From a design standpoint, however, integrating circuits on multiple chips in a multi-layer semiconductor stack can be problematic. Laying out signal paths and electrical conductors to effectively interconnect circuits conventionally has required substantial design work, and opportunities for design reuse have been limited.
Another challenge for multi-layer semiconductor stacks is thermal dissipation. Conventionally, heat is dissipated from semiconductor chips through the use of heat sink arrangements that are mounted to the surfaces of chips to conduct heat away from the chips. With the circuit layers on such chips typically mounted in a face-down manner to electrically interconnect the circuit layers to circuit boards or packages, heat sinks are typically mounted to the opposite faces of such chips from that upon which circuit layers have been formed, requiring heat to be transferred through the silicon or other semiconductor substrates to the heat sinks.
With conventional single-layer semiconductor chips, and considering the relatively poor thermal conductivity of the semiconductor substrate, thermal dissipation is improved by maximizing the surface area of a chip that is contacted by a heat sink. However, with multi-layer semiconductor stacks, the same amount of logic circuitry, and thus the same amount of heat generating circuitry, can present a much smaller surface area to which a heat sink may be mounted. A four layer semiconductor stack, for example, including logic circuitry disposed over four circuit layers, would present one fourth of the surface area that would be presented were the same logic circuitry disposed in a single layer semiconductor chip. As a result, the four layer semiconductor stack would have roughly 4× the thermal density of a single layer chip.
Therefore, a significant need exists in the art for an improved manner of dissipating heat in a multi-layer semiconductor stack.